A variety of techniques are available to assemble microelectronic die, such as an integrated circuit device (commonly referred to as an IC chip), into a component or a package. One type of packaging employs a flip chip package, such as a C4 flip chip package, to mount the die onto a package substrate. In one such flip chip packaging technique, a dielectric material, such as a low-dielectric constant (low-k) material layer, is used in-between the metal layers on the active die side for higher electrical performance and contact pads or bumps reside along the surface to mate the conductive contacts (terminals) to electrically join the die to the package substrate. A joint forms at the mating of the electrical conductive paths. In order to assemble the die onto the package substrate, a common technique is to employ a sequence of operative stages that subject the two components to significant temperature variations.
For example, in one die to substrate assembly technique the sequence of stages practiced includes the following: 1) die placement 2) solder reflow 3) deflux 4) prebake 5) underfill dispense 6) underfill cure. In this example sequence, significant temperature differentials are experienced between some of the stages. In the example technique, die placement typically occurs at room temperature (25° C.) but the temperature of the joint rises to approximately 221° C. during the solder reflow stage. The solder reflow is used to electrically join the electrical contacts of the die and the package substrate. After the electrical bonding of the die to the substrate, the assembled unit is allowed to cool to room temperature prior to commencing the next stage, which is the deflux stage. The cooling usually is encountered, since the solder reflow operation occurs in one equipment while deflux is performed in another. Typically, the substrate with the die is transported from one equipment to the other, allowing ample time for the electrical contacts to cool from about 221° C. (temperature of solder reflow) to room temperature (approximately 25° C.). In some instances the lag period may not be avoided, since solder reflow operation is performed on single units, while the deflux operation is performed on multiple assembled units in a batch process. The assembled units cool from the higher temperatures encountered at the solder reflow while waiting to be stacked and transported to the equipment which performs the deflux operation. In a typical deflux operation, the temperature is again raised to approximately in the range of 80° C.
Once the deflux stage has been completed to remove unwanted flux residue, the assembled units are then transported to another equipment to perform the prebake operation. Again at this point the assembled units are lowered to the room temperature of 25° C. for transport before the prebake operation is performed. In one prebake operation, the packaged assemblies are raised to a temperature range of approximate 163° C. Subsequently, underfill dispense is performed to fill the void area between the die and the substrate with the underfill material. Then, the underfill is allowed to cure in the sixth stage. In one practice, the underfill dispense is performed at about 110° C. and subsequently the assembly is allowed to cool to room temperature, after which the underfill cure is performed at about 163° C.
In the above example, the die and substrate assembly undergo considerable temperature changes as it sequences through the six operative stages. One of the more significant temperature differential occurs when the solder reflow is performed on the assembly (at about 221° C.) and subsequently allowed to cool to room temperature. A temperature differential of approximately 195° C.-200° C. may be encountered when the assembly is allowed to cool after the reflow operation. As noted, the first five stages occur without the underfill protection residing between the die and substrate and only the last step (underfill cure) is performed with the underfill support between the die and the substrate. Also, during the first five operative stages, where no underfill protection is provided, the assembly undergoes various temperature changes including three occasions at which point the die and substrate assembly are allowed to cool to room temperature. Again the most likely point for the biggest temperature differential occurs after the solder reflow.
Because the cooling of the assembly to the ambient or room temperature may occur several times before the underfill material supports the die on the substrate, there is a tendency for the dielectric material of the die (as well as the substrate) to experience cracking or delamination. Such cracking or delamination may be enhanced if the dielectric material is a low k dielectric such as a low-k dielectric layer, typically used for inter-level dielectric (ILD). The temperature changes may cause considerable thermal stress, especially in the instance where the coefficient of thermal expansion (CTE) differs significantly for the materials present. In the particular case, CTE mismatch is between the silicon and the dielectric material.